Solidigm announces NAND PLC - 5-bit/cell storage, SSDs will get cheaper and cheaper
The PLC will be the QLC serial high-density NAND memory and it will pave the way for high- capacity SSDs that are even cheaper than the current QLC. PLC NAND (Penta-Level Cell) technology was introduced by Solidigm - the NAND memory research and production arm sold by Intel to SK Hynix at the Flash Memory Summit 2022. As the name suggests, Penta-Level Cell will allow store 5 bits of data/memory cell, QLC is 4 bits while TLC is 3 bits. SSDs using PLC NAND are expected to hit the market before 2025 .
To do this, the PLC adds voltage states. As SLC has only 2 voltage states, on or off, which shows 2 values as 1 or 0, MLC has 4 voltage states so that each memory cell can store 4 values as 00 01 10 11 ( 2 bits/cell). TLC has 8 voltage states to represent 8 values (3 bits/cell), QLC has 16 voltage states (4 bits/cell) and PLC has up to 32 states (5 bits/cell).
The obvious advantage is storage density, but in return, the memory cell will be less durable, thereby affecting the overall durability of the SSD. QLC with 16 voltage states is generally less reliable than TLC because the smaller voltage difference makes the read/write process more susceptible to noise, thereby increasing the data error rate. In addition, QLC has a lower write and erase cycle than TLC, so drives using QLC NAND should be used as storage in the write-once, read-many fashion. The story will continue with the PLC as the difference in voltage levels will be smaller, the memory cell will be under more pressure and the microcontroller will need to have stronger error correction algorithms to limit the error rate. data. The durability of PLC will also be lower than that of QLC.
Still, Solidigm seems very confident in PLC NAND. As an Intel subsidiary, Solidigm uses Intel NAND's signature floating gate semiconductor design, and the company says this semiconductor design is suitable for increasing the number of bits that each memory cell can store, thereby allowing the maker of the NAND PLC.
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